Packages with multi-thermal interface materials and methods of fabricating the same

ABSTRACT

A package includes a die on a surface of a package component. The package also includes a first die stack on the surface of the package component. The package further includes a first thermal interface material (TIM) having a first thermal conductivity and disposed on the first die stack. In addition, the package includes a second thermal interface material (TIM) having a second thermal conductivity and disposed on the die. The first thermal conductivity of the first TIM is different from the second thermal conductivity of the second TIM.

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims the benefit of U.S. Provisional Application No.62/770,223, filed on Nov. 21, 2018, the entirety of which isincorporated by reference herein.

BACKGROUND

The integrated circuit (IC) industry has experienced exponential growth.Technological advances in IC materials and design have producedgenerations of ICs, wherein each generation has smaller and more complexcircuits than the previous generation. In the course of IC evolution,functional density (i.e., the number of interconnected devices per chiparea) has generally increased while geometric size (i.e., the smallestcomponent (or line) that can be created using a fabrication process) hasdecreased. This scaling-down process generally provides benefits byincreasing production efficiency and lowering associated costs. Suchscaling-down has also increased the complexity of processing andmanufacturing ICs.

When more devices are placed in one chip, the design complexity alsoincreases. One solution to solve the problems discussed above is tostack dies on top of one another and interconnect or route them throughconnections. Such a configuration is named a three-dimensionalintegrated circuit (3DIC). Some of the benefits of 3DIC includeexhibiting a smaller footprint, reducing power consumption by reducingthe lengths of signal interconnects, and improving yield and fabricationcost if individual dies are tested separately prior to assembly.Although existing methods of fabricating 3DIC packages have beengenerally adequate for their intended purposes, they have not beenentirely satisfactory in all respects.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It shouldbe noted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A, 2A, 3A-1, 3A-2, 4A and 5A are top views of intermediatestructures at various stages of an exemplary method of forming apackage, in accordance with some embodiments.

FIGS. 1B, 1D, 1E, 2B, 2C, 3B, 4B, 5B-1 and 5B-2 are cross-sectionalviews of intermediate structures at various stages of an exemplarymethod for forming a package, along line B-B in FIGS. 1A, 2A, 3A-1,3A-2, 4A and 5A, in accordance with some embodiments.

FIG. 1C is a detailed cross-sectional view of an interposer, inaccordance with some embodiments.

FIG. 4C is an enlarged cross-sectional view of the region C in FIG. 4B,in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the subject matterprovided. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as “under,” “beneath,”“below,” “lower,” “over,” “above,” “upper” and the like, may be usedherein for ease of description to describe one element or feature'srelationship to another element(s) or feature(s) as illustrated in thefigures. The spatially relative terms are intended to encompassdifferent orientations of the device in use or operation in addition tothe orientation depicted in the figures. The apparatus may be otherwiseoriented (rotated 90 degrees or at other orientations) and the spatiallyrelative descriptors used herein may likewise be interpretedaccordingly.

Other features and processes may also be included. For example, testingstructures may be included to aid in the verification testing of the 3Dpackaging or 3DIC devices. The testing structures may include, forexample, test pads formed in a redistribution layer or on a substratethat allows the testing of the 3D packaging or 3DIC devices, the use ofprobes and/or probe cards, and the like. The verification testing may beperformed on intermediate structures as well as the final structure.Additionally, the structures and methods disclosed herein may be used inconjunction with testing methodologies that incorporate intermediateverification of known good dies to increase the yield and decreasecosts.

Embodiments disclosed herein relate generally to packages withmulti-thermal interface materials. The multi-thermal interface materialsmay be dispensed on different dies or die stacks of the whole package byusing different dispensers. The multi-thermal interface materialsdispensed on different dies or die stacks by using different dispenserscan enhance the throughput of fabricating packages. According to theembodiments of the disclosure, a thermal interface material that has arelatively high thermal conductivity is dispensed on a high-powerconsuming die or die stack. Therefore, the heat dissipation of the wholepackage is improved.

Moreover, the multi-thermal interface materials dispensed on differentdies or die stacks of the whole package can avoid or reduce stressconcentration phenomenon. According to the embodiments of thedisclosure, a thermal interface material that has fillers with arelatively large particle size may be dispensed on dies or die stackslocated at the peripheral region of the package. The whole thickness ofthe multi-thermal interface materials depends on the relatively largeparticle sized fillers in the thermal interface material and becomesthick. The warpage variation of the package is thereby decreased toreduce stress concentration phenomenon of packages. Therefore, somedefects of packages, for example, die crack or low-k dielectric layerdelamination are prevented. Accordingly, the reliability of the packagesis enhanced.

The foregoing broadly outlines some aspects of the embodiments describedherein. Some embodiments described herein are described in the contextof 3DIC packages or 2.5DIC packages. Some variations of the exemplarymethods and structures are described in the embodiments of thedisclosure. A person having ordinary skill in the art will readilyunderstand other modifications may be made that are contemplated withinthe scope of other embodiments. Although embodiments of the method maybe described in a particular order, various other embodiments of themethod may be performed in any logical order and may include fewer ormore steps than what is described herein.

FIGS. 1A, 2A, 3A-1, 3A-2, 4A and 5A illustrate top views of intermediatestructures at various stages of an exemplary method of forming a package100, in accordance with some embodiments. The package 100 may be a 2D(two-dimensional) IC package, a 2.5DIC package or a 3DIC package. The2.5DIC package is a 2DIC package incorporating with an interposer. The3DIC package is for example a chip-on-wafer-on-substrate (CoWoS)package. In some embodiments, the package 100 is illustrated using a3DIC package. FIGS. 1B, 1D, 1E, 2B, 2C, 3B, 4B, 5B-1 and 5B-2 illustratecross-sectional views of intermediate structures at various stages of anexemplary method for forming a package 100, along line B-B in FIGS. 1A,2A, 3A-1, 3A-2, 4A and 5A, in accordance with some embodiments.

FIG. 1A is a top view of an initial package structure 50 at a stage ofan exemplary method of forming a package 100, in accordance with someembodiments. The initial package structure 50 includes multiple dies,multiple die stacks or a combination thereof. In some embodiments, theinitial package structure 50 includes one die or die stack 10 and fourdie stacks 12 around the die or die stack 10 in the top view of FIG. 1A.In some other embodiments, the initial package structure 50 includes onedie or die stack 10 and four dies 13 around the die or die stack 10 inthe top view of FIG. 1A. The initial package structure 50 may includeany number of dies and/or die stacks, and is not limited to the numberof dies and/or die stacks in FIG. 1A. In addition, the layout of thedies and/or die stacks in the packages 100 is not limited to that ofFIG. 1A.

FIG. 1B is a cross-sectional view of an initial package structure 50along line B-B in FIG. 1A, in accordance with some embodiments. Theinitial package structure 50 may be a chip-on-wafer (CoW) package. Theinitial package structure 50 may include a die 10 disposed between twodie stacks 12 (sometimes referred to as chips 10 and 12). In someembodiments, the die 10 is a high-power consuming die and the die stacks12 are low-power consuming die stacks. The die 10 may consume arelatively high amount of power, and hence generate a relatively largeamount of heat, compared to the die stacks 12. For example, a high-powerconsuming die 10 may consume between about 50 W and about 100 W ofpower. A low-power consuming die stack 12 may consume between about 5 Wand about 10 W of power.

In some embodiments, the die 10 may be a single system on chip (SoC) dieor a logic die, which may further be a Central Processing Unit (CPU), aGraphics Processing Unit (GPU), or the like. In some embodiments, thedie stacks 12 may be high bandwidth memory (HBM) and/or high memory cube(HMC) modules, which may include multiple memory dies 12 b bonded to alogic die 12 a, as shown in FIG. 1B in accordance with some embodiments.In alternative embodiments, the die 10 and the die stacks 12 may beother chips having other functions.

Referring to FIGS. 1A and 1B, the die 10 and the die stacks 12 areencased in a molding compound 16, in accordance with some embodiments.As shown in FIG. 1A, the molding compound 16 may form a full ringencircling the die 10 and the die stacks 12, in accordance with someembodiments. In alternative embodiments, the molding compound 16 doesnot form a full ring, and may include a single piece or a plurality ofdiscrete pieces. As shown in FIG. 1B, the top surface of the die 10 iscoplanar with the top surface of the molding compound 16, in accordancewith some embodiments. Also, the top die 12 b in the die stacks 12 has atop surface that is coplanar with the top surface of the moldingcompound 16. The top surfaces of the die 10 and the die stacks 12 areexposed through the molding compound 16.

The die 10 and the die stacks 12 are bonded to a top surface of apackage component such as an interposer 18 through a plurality ofconnectors 14, as shown in FIG. 1B in accordance with some embodiments.The connectors 14 may be micro-bumps. In alternative embodiments, thedie 10 and the die stacks 12 may be bonded to a different packagecomponent such as a substrate, a printed circuit board (PCB), or thelike. The interposer 18 may be a wafer having an interconnect structurefor electrically connecting active devices (not shown) in the die 10 andthe die stacks 12 to form functional circuits.

FIG. 1C illustrates a detailed cross-sectional view of an interposer 18in accordance with some embodiments. A connector 14 of the die 10 or thedie stack 12 is electrically connected to a contact pad 22 on a top sideof the interposer 18. A passivation layer 24 may extend over a topsurface of the interposer 18 and cover edge portions of the contact pad22. The contact pad 22 is disposed in a dielectric layer 27 and iselectrically connected to metallization layers 26. The metallizationlayers 26 may include metal lines 28 a and vias 28 b formed in multipledielectric layers 27. The dielectric layers 27 are made of a dielectricmaterial, for example a low-k dielectric material having a k-value lowerthan about 4.0 or an extra-low-k (ELK) dielectric material having ak-value lower than about 2.8. A through-substrate via (TSV) 30 mayelectrically connect the metallization layer 26 to a connector 20 on abackside of the interposer 18. The TSV 30 is formed to pass through asubstrate 29 of the interposer 18.

In some embodiments, the connectors 20 on the backside of the interposer18 may be controlled collapse chip connection (C4) bumps, which includesolder balls. The connectors 20 may have a larger critical dimension(e.g., pitch) than that of the connectors 14. For example, theconnectors 20 may have a pitch of about 100 μm while the connectors 14may have a pitch of about 40 μm. The interposer 18 may further have anunder-bump metallurgy (UBM) 32 connected to the connector 20 and apassivation layer 34 on the backside of the interposer 18. Otherconfigurations of the interposer 18 may also be used.

FIG. 1D is a cross-sectional view of an initial package structure 50 ata stage of an exemplary method of forming the package 100, along lineB-B in FIG. 1A, in accordance with some other embodiments. The initialpackage structure 50 of FIG. 1D is used in a 2.5DIC package, and mayinclude a die 10 disposed between two dies 13 (sometimes referred to aschips 10 and 13). In some embodiments, the die 10 is a high-powerconsuming die and the dies 13 are low-power consuming dies. The die 10may consume a relatively high amount of power, and hence generate arelatively large amount of heat, compared to the dies 13. For example, ahigh-power consuming die 10 may consume between about 50 W and about 100W of power. A low-power consuming die 13 may consume between about 5 Wand about 10 W of power.

In some embodiments, the die 10 may be a single system on chip (SoC) dieor a logic die, which may further be a Central Processing Unit (CPU), aGraphics Processing Unit (GPU), or the like. In some embodiments, thedies 13 may be memory dies. In alternative embodiments, the die 10 andthe dies 13 may be other chips having other functions.

Referring to FIGS. 1A and 1D, the die 10 and the dies 13 are encased ina molding compound 16, in accordance with some embodiments. As shown inthe top view of FIG. 1A, the molding compound 16 may form a full ringencircling the die 10 and the dies 13, in accordance with someembodiments. In alternative embodiments, the molding compound 16 doesnot form a full ring, and may include a single piece or a plurality ofdiscrete pieces. As shown in the cross-sectional view of FIG. 1D, thetop surface of the die 10 is coplanar with the top surface of themolding compound 16, in accordance with some embodiments. Also, the dies13 have top surfaces that are coplanar with the top surface of themolding compound 16. Therefore, the top surfaces of the die 10 and thedies 13 are exposed through the molding compound 16.

The die 10 and the dies 13 are bonded to a top surface of a packagecomponent such as an interposer 18 through a plurality of connectors 14,as shown in FIG. 1D in accordance with some embodiments. The connectors14 may be micro-bumps. The interposer 18 may be a wafer having aninterconnect structure for electrically connecting active devices (notshown) in the die 10 and the dies 13 to form functional circuits. Thedetailed structure of the interposer 18 may be the same as or similar tothose described above with respect to the interposer 18 of FIG. 1C. Inalternative embodiments, the package 100 is a 2DIC package and theinterposer 18 of FIG. 1D is omitted. The die 10 and the dies 13 arebonded to a different package component such as a substrate, a printedcircuit board (PCB), or the like.

FIG. 1E is a cross-sectional view of an initial package structure 50 ata stage of an exemplary method of forming the package 100 along line B-Bin FIG. 1A, in accordance with some embodiments. The initial packagestructure 50 of FIG. 1E is a CoW package for a 3DIC package, and mayinclude a die stack 10 disposed between two die stacks 12 (sometimesreferred to as chips 10 and 12).

The die stack 10 may be multiple stacked dies, for example a die 10-1stacked on a die 10-2. In some embodiments, each of the dies 10-1 and10-2 is a high-power consuming die and the die stacks 12 are low-powerconsuming die stacks. The dies 10-1 and 10-2 may consume a relativelyhigh amount of power, and hence generate a relatively large amount ofheat, compared to the die stacks 12. For example, a high-power consumingdie 10-1 or 10-2 may consume between about 50 W and about 100 W ofpower. A low-power consuming die stack 12 may consume between about 5 Wand about 10 W of power.

In some embodiments, each of the dies 10-1 and 10-2 may be a singlesystem on chip (SoC) die or a logic die, which may further be a CentralProcessing Unit (CPU), a Graphics Processing Unit (GPU), or the like. Insome embodiments, the die stacks 12 may be high bandwidth memory (HBM)and/or high memory cube (HMC) modules, which may include multiple memorydies 12 b bonded to a logic die 12 a, as shown in FIG. 1E in accordancewith some embodiments. In alternative embodiments, the die stack 10 andthe die stacks 12 may be other chips having other functions.

Referring to FIGS. 1A and 1E, the die stack 10 and the die stacks 12 areencased in a molding compound 16, in accordance with some embodiments.As shown in the top view of FIG. 1A, the molding compound 16 may form afull ring encircling the die stack 10 and the die stacks 12, inaccordance with some embodiments. In alternative embodiments, themolding compound 16 does not form a full ring, and may include a singlepiece or a plurality of discrete pieces. As shown in the cross-sectionalview of FIG. 1E, the top die 10-1 of the die stack 10 has a top surfacethat is coplanar with the top surface of the molding compound 16, inaccordance with some embodiments. Also, the top die 12 b in the diestacks 12 has a top surface that is coplanar with the top surface of themolding compound 16. The top surfaces of the top die 10-1 of the diestack 10 and the top dies 12 b of the die stacks 12 are exposed throughthe molding compound 16.

The die stack 10 and the die stacks 12 are bonded to a top surface of apackage component such as an interposer 18 through a plurality ofconnectors 14, as shown in FIG. 1E in accordance with some embodiments.The connectors 14 may be micro-bumps. In alternative embodiments, thedie stack 10 and the die stacks 12 may be bonded to a different packagecomponent such as a substrate, a printed circuit board (PCB), or thelike. The interposer 18 may be a wafer having an interconnect structurefor electrically connecting active devices (not shown) in the die stack10 and the die stacks 12 to form functional circuits. The detailedstructure of the interposer 18 may be the same as or similar to thosedescribed above with respect to the interposer 18 of FIG. 1C.

Next, referring to FIGS. 2A and 2B, the initial package structure 50 ofFIG. 1B, such as a CoW package, is bonded to a substrate 52 using theconnectors 20 for forming a package 100, in accordance with someembodiments. FIG. 2A is a top view of an intermediate structure at astage of an exemplary method of forming the package 100, and FIG. 2B isa cross-sectional view along line B-B in FIG. 2A, in accordance withsome embodiments. The package 100 may be a chip-on-wafer-on-substrate(CoWoS) package. In alternative embodiments, the initial packagestructure 50 of FIG. 1D or 1E is bonded to a substrate 52 using theconnectors 20 to form another package 100. A reflow process is performedto reflow and bond the connectors 20 to the substrate 52. In theembodiments of FIGS. 2B, 2C, 3B, 4B, 5B-1 and 5B-2, the initial packagestructure 50 of FIG. 1B is illustrated as an exemplary structure. Inalternative embodiments, the initial package structures 50 of FIGS. 1Dand 1E may be used to bond with the substrate 52 for forming otherpackages 100.

In some embodiments, the substrate 52 may be a printed circuit board(PCB), an organic substrate, a ceramic substrate, a motherboard, or thelike. The substrate 52 may be used to interconnect the initial packagestructures 50 with other packages and/or devices to form functionalcircuits. The other packages and/or devices may be multiple passivedevices 53, such as capacitors, resistors, inductors, varactors, and/orthe like. The passive devices 53 may also be electrically connected tothe interposer 18 through the substrate 52 and the connectors 20.Alternatively, die stacks 10 and 12 and the passive devices 53 may beattached to an organic or ceramic substrate. As shown in FIGS. 2A and2B, the multiple passive devices 53 are attached to the top surface ofthe substrate 52 and around the periphery of the initial packagestructures 50 in accordance with some embodiments. Moreover, the initialpackage structure 50 is also attached to the top surface of thesubstrate 52.

In addition, the package 100 may further include contacts 54 disposed onthe bottom surface of the substrate 52, as shown in FIG. 2B inaccordance with some embodiments. The contacts 54 are disposed oppositeto the initial package structure 50 and the passive devices 53. Thecontacts 54 may be ball grid array (BGA) balls. The contacts 54 may beused to electrically connect the package 100 such as a CoWoS package toa motherboard (not shown) or another device component of an electricalsystem.

Next, an underfill material 56 may be dispensed between the initialpackage structure 50 and the substrate 52, as shown in FIG. 2C inaccordance with some embodiments. The underfill material 56 may be asilica filled epoxy resin, and may be used to fill the gap space betweenthe initial package structure 50 and the substrate 52. The underfillmaterial 56 may be injected into the gap space using a nozzle that ismoved around the initial package structure 50. The underfill material 56may increase mechanical reliability by distributing stresses across thetop surface of the substrate 52 rather than allowing them to becomeconcentrated in the connectors 20. In addition, the underfill material56 may provide encapsulation from moisture and contaminants in theexternal environment. In alternative embodiments, the underfill material56 may be omitted. A molding compound (not shown) may be used to fillthe gap space between the initial package structure 50 and the substrate52.

Next, referring to FIG. 3A-1, an adhesive 60 is dispensed on the topsurface of the substrate 52, and a first thermal interface material(TIM) 62 is dispensed on the die stacks 12 of the initial packagestructure 50, in accordance with some embodiments. The adhesive 60 isdispensed on the peripheral area of the substrate 52 to encircle thepassive devices 53 and the initial package structure 50. As shown in thetop view of FIG. 3A-1, the adhesive 60 does not form a full ring, andmay include a plurality of discrete pieces, in accordance with someembodiments. Alternatively, the adhesive 60 forms a full ring toencircle the passive devices 53 and the initial package structure 50, asshown in FIG. 3A-2 in accordance with some embodiments. FIG. 3Billustrates a cross-sectional view of an intermediate structure forforming the package 100 along line B-B in FIGS. 3A-1 and 3A-2, inaccordance with some embodiments.

In some embodiments, the first TIM 62 and the adhesive 60 are made ofthe same material and can be dispensed by using the same dispenser. Thematerial of the adhesive 60 and the first TIM 62 includes a basematerial and fillers dispersed in the base material. The base materialmay be a polymer such as epoxies, urethane, polyurethane, siliconeelastomers or the like. The fillers are such as particles made ofaluminum oxide, boron nitride, aluminum nitride or the like. The firstTIM 62 is dispensed on the die stacks 12 and/or the dies 13. The diestacks 12 and/or the dies 13 consume a relatively low amount of power,and hence generate less heat than the die or die stack 10.

The first TIM 62 may be dispensed to a pattern of a plurality of stripsas shown in FIGS. 3A-1 and 3A-2 in accordance with some embodiments. Thewidth and the length of the strips, and the space between the strips ofthe first TIM 62 are determined by the area size of the dies 13 and/orthe die stacks 12. In some examples, the thickness of the dispensedstrips of the second TIM 64 is in a range from about 5 μm to about 500μm, for example about 100 μm. In some examples, the first TIM 62 may bedispensed across about 50% to about 100% of the area of the dies 13and/or the die stacks 12. The dispensed strips of the first TIM 62 donot completely occupy all area of the dies 13 and/or the die stacks 12.

Next, referring to FIGS. 4A and 4B, a second thermal interface material(TIM) 64 is dispensed on the die or die stack 10 of the initial packagestructure 50, in accordance with some embodiments. The die or die stack10 consumes a relatively high amount of power, and hence generate arelatively large amount of heat, compared to the dies 13 and/or the diestacks 12. The second TIM 64 on the high-power consuming die or diestack 10 has a thermal conductivity that is higher than the thermalconductivity of the first TIM 62 on the low-power consuming dies 13 ordie stacks 12. In some examples, the thermal conductivity of the firstTIM 62 and the thermal conductivity of the adhesive 60 are in a rangefrom about 0.5 W/mK to about 2 W/mK. The thermal conductivity of thesecond TIM 64 is in a range from about 10 W/mK to about 50 W/mK.

In some embodiments, the material of the second TIM 64 includes a basematerial and thermal conductive fillers dispersed in the base material.The base material includes a polymer such as silicone resin, epoxy resinor the like, which has a good thermal conductivity in a range from about3 watts per meter kelvin (W/mK) to about 5 W/mK. The thermal conductivefillers in the second TIM 64 include particles made of aluminum oxide,boron nitride, aluminum nitride, aluminum, copper, silver, indium,nickel or a combination thereof. In other embodiments, the second TIM 64includes other materials such as a metallic-based or solder-basedmaterial containing silver, indium paste, or the like.

FIG. 4B illustrates a cross-sectional view of an intermediate structureof forming the package 100 along line B-B in FIG. 4A, after the firstTIM 62 and the second TIM 64 are dispensed on the initial packagestructure 50, in accordance with some embodiments. FIG. 4C is anenlarged cross-sectional view of a region C in FIG. 4B, in accordancewith some embodiments. The particle size of the fillers 62 f in thefirst TIM 62 is larger than the particle size of the thermal conductivefillers 64 f in the second TIM 64. In some examples, the particle sizeof the fillers 62 f in the first TIM 62 is in a range from about 5 timesto about 20 times larger than the particle size of the thermalconductive fillers 64 f in the second TIM 64.

The second TIM 64 may be also dispensed to a pattern of a plurality ofstrips, as shown in FIG. 4A in accordance with some embodiments. Thedispensed strips of the second TIM 64 may be a continuous pattern. Thewidth and the length of the strips, and the space between the strips ofthe second TIM 64 are determined by the area size of the die or diestack 10. In some examples, the thickness of the dispensed strips of thesecond TIM 64 is in a range from about 5 μm to about 500 μm, for exampleabout 100 μm. In some examples, the second TIM 64 may be dispensedacross about 80% to about 100% of the area of the die or die stack 10.The dispensed strips of the second TIM 64 do not completely occupy allarea of the die or die stack 10.

Afterwards, referring to FIGS. 5A and 5B-1, a lid 70 is attached on theinitial package structure 50 through the first TIM 62 and the second TIM64, and the lid 70 is also attached on the substrate 52 through theadhesive 60, in accordance with some embodiments. FIG. 5A is a top viewof the lid 70 attached on the initial package structure 50 to form thepackage 100, in accordance with some embodiments. FIG. 5B-1 is across-sectional view of the package 100 along line B-B in FIG. 5A, inaccordance with some embodiments. After the lid 70 is attached on theinitial package structure 50, the first TIM 62 and the second TIM 64have the same thickness and fill the space between the lid 70 and theinitial package structure 50. Moreover, the thickness of the second TIM64 depends on the particle size of the fillers 62 f (FIG. 4C) in thefirst TIM 62 since the particle size of the fillers 62 f is larger thanthe particle size of the thermal conductive fillers 64 f (FIG. 4C) inthe second TIM 64.

In some embodiments, the lid 70 is a heat dissipating lid which includesa top portion 70T and a ring portion 70R. The bottom surface of the topportion 70T is in contact with the first TIM 62 and the second TIM 64.The bottom surface of the ring portion 70R is in contact with theadhesive 60 to adhere the lid 70 to the substrate 52. The top view ofthe ring portion 70R may form a ring encircling the die or die stack 10and the dies 13 or the die stacks 12 of the initial package structure50. In alternative embodiments, the ring portion 70R may form a partialring, or may include a plurality of separated pieces. The lid 70 mayhave a high thermal conductivity, for example in a range from about 200W/mK to about 400 W/mK or more, and may be made of a metal or a metalalloy. In some examples, the material of the lid 70 is such as Al, Cu,Ni, Co, alloy thereof, or a combination thereof.

After the lid 70 is attached on the substrate 52 to encapsulate theinitial package structure 50, the first TIM 62 and the second TIM 64 maycompletely occupy the space between the top portion 70T of the lid 70and the initial package structure 50, as shown in FIG. 5B-1 inaccordance with some embodiments. In some other embodiments, the firstTIM 62 and the second TIM 64 may partially occupy the space between thetop portion 70T of the lid 70 and the initial package structure 50.There may be a gap presented in the first TIM 62 and the second TIM 64.In addition, after the lid 70 is attached on the substrate 52, thepassive devices 53 are positioned between the ring portion 70R of thelid 70 and the substrate 52. Moreover, the passive devices 53 aredisposed between the adhesive 60 and the initial package structure 50.In the package 100, the die or die stack 10, the dies 13 and/or the diestacks 12, and the passive devices 53 are encapsulated and protected bythe lid 70, the first TIM 62, the second TIM 64, and the adhesive 60.

FIG. 5B-2 illustrates a cross-sectional view of the package 100 alongline B-B in FIG. 5A, in accordance with some embodiments. The package100 includes a heat dissipating ring 72 attached on the substrate 52using the adhesive 60. Thereafter, a lid 70 is attached on the heatdissipating ring 72 using an additional adhesive 66. In some instances,the adhesive 60 and the additional adhesive 66 may be made of the samematerial. In some other instances, the material of the adhesive 60 maybe different from that of the additional adhesive 66. The lid 70 is alsoattached on the initial package structure 50 using the first TIM 62 andthe second TIM 64.

In some embodiments, the lid 70 may be made of a metal or a metal alloy,for example Al, Cu, Ni, Co, alloy thereof, or a combination thereof. Insome instances, the heat dissipating ring 72 may be made of a thermalconductive material that is different from the material of the lid 70.The material of the heat dissipating ring 72 is for example siliconcarbide, aluminum nitride, graphite, and the like. In some instances,the heat dissipating ring 72 may be made of the same material as the lid70. In the embodiments, the passive devices 53 are positioned betweenthe lid 70 and the substrate 52 and encircled by the heat dissipatingring 72. In addition, the passive devices 53 are disposed between theadhesive 60 and the initial package structure 50.

In some embodiments, the first TIM 62, the adhesive 60 and theadditional adhesive 66 are made of the same material. The first TIM 62and the adhesive 60 are dispensed by using a first dispenser in the sameprocess step. The additional adhesive 66 is dispensed by using the firstdispenser in another process step. Next, the second TIM 64 is dispensedby using a second dispenser. In some other embodiments, the first TIM62, the adhesive 60 and the additional adhesive 66 are made of the samematerial. The adhesive 60 is dispensed by using a first dispenser. Thefirst TIM 62 and the additional adhesive 66 are dispensed by using thefirst dispenser in the same process step. Thereafter, the second TIM 64is dispensed by using a second dispenser.

In the embodiments, after the lid 70 is attached on the initial packagestructure 50, the first TIM 62 and the second TIM 64 have the samethickness. Moreover, the thickness of the second TIM 64 depends on theparticle size of the fillers 62 f (FIG. 4C) in the first TIM 62 sincethe particle size of the fillers 62 f is larger than the particle sizeof the thermal conductive fillers 64 f (FIG. 4C) in the second TIM 64.Therefore, the thickness of the second TIM 64 of the embodiments of thedisclosure becomes thicker than using a single second TIM 64 dispensedon the whole area of the initial package structure 50.

In the development of IC industry, the package size becomes bigger andbigger as more and more system in package (SiP) technology applicationsare needed. The throughput of fabricating IC packages is difficult toenhance due to a fabrication bottleneck in the TIM dispensing process onthe dies or die stacks. In some embodiments, the adhesive 60 and thefirst TIM 62 are made of the same material and can be dispensed by usingthe same dispenser in the same process step. The second TIM 64 can bedispensed on the remaining area of the initial package structure 50 byusing another dispenser. The bottleneck in the fabrication process thatoccurs in the TIM dispensing process can be eliminated, and the time ittakes to fabricate the packages 100 is reduced. Therefore, thethroughput of fabricating the packages 100 according the embodiments ofthe disclosure is higher than that of fabricating packages by using adispenser for dispensing a single TIM on the whole area of the initialpackage structure.

In some other embodiments, the adhesive 60 and the first TIM 62 may bemade of different materials. The adhesive 60 may be dispensed on thesubstrate 52 by using a first dispenser. The first TIM 62 may bedispensed on the dies 13 and/or the die stacks 12 by using a seconddispenser. The second TIM 64 may be dispensed on the die or die stack 10by using a third dispenser. The throughput of fabricating the packages100 according the embodiments of the disclosure is still higher thanthat of fabricating packages by using a dispenser for dispensing asingle TIM on the whole area of the initial package structure.

In some embodiments, the initial package structure 50 may include afirst die or die stack that consumes a relatively low amount of power,and hence generate less heat. The initial package structure 50 may alsoinclude a second die or die stack that consumes a higher amount of powerthan the first die or die stack, and hence generate a larger amount ofheat than the first die or die stack. The initial package structure 50may further include a third die or die stack that consumes a higheramount of power than the second die or die stack, and hence generates alarger amount of heat than the second die or die stack. A first TIM maybe dispensed on the first die or die stack. A second TIM may bedispensed on the second die or die stack. A third TIM may be dispensedon the third die or die stack. In some embodiments, the first TIM has afirst thermal conductivity that is lower than the second thermalconductivity of the second TIM. Moreover, the second thermalconductivity of the second TIM is lower than a third thermalconductivity of the third TIM.

In some embodiments, the first TIM and the adhesive may be made of thesame material and are dispensed by using a first dispenser. The secondTIM and the third TIM may be dispensed by using a second dispenser and athird dispenser, respectively. According to the embodiments of thedisclosure, the first, second and third TIMs on the whole area of theinitial package structure 50 can be dispensed by using the first, secondand third dispensers, respectively. Therefore, the throughput offabricating the packages 100 according the embodiments of the disclosureis enhanced.

In some other embodiments, the first TIM and the adhesive may be made ofthe same material and are dispensed by using a first dispenser. Thesecond TIM and the third TIM may be made of the same material and aredispensed by using a second dispenser. The throughput of fabricating thepackages 100 according the embodiments of the disclosure is alsoenhanced.

In some embodiments, the dispensing patterns of the first TIM 62 and thesecond TIM 64 may be continuous strips as shown in FIG. 4A. In someother embodiments, the dispensing pattern of the first TIM 62 may bedifferent from the dispensing pattern of the second TIM 64, and thosepatterns are not limited to a plurality of strips. In addition, thelayout of the dies or die stacks that consume different amounts of poweris not limited in that of FIG. 1A. In some embodiments, a high-powerconsuming die or die stack 10 may be positioned in the center region ofthe initial package structure 50. A low-power consuming die 13 or diestack 12 may be positioned in the peripheral region of the initialpackage structure 50. In some embodiments, a high-power consuming die ordie stack 10 may be positioned in a region of the initial packagestructure 50, such as a corner region or an edge region, and a low-powerconsuming die 13 or die stack 12 may be positioned in another region ofthe initial package structure 50.

In some embodiments, the first TIM 62 including fillers 62 f of a largeparticle size (FIG. 4C) is dispensed on the low-power consuming die 13or die stack 12 in the peripheral region of the initial packagestructure 50. The second TIM 64 including fillers 64 f of a smallparticle size (FIG. 4C) is dispensed on the high-power consuming die ordie stack 10 in the center region of the initial package structure 50.The small particle sized fillers 64 f of the second TIM 64 can increasecontact area of the fillers 64 f to enhance heat spreading effect.Therefore, the second TIM 64 having the small particle sized fillers 64f can provide a higher thermal conductivity than the first TIM 62 havingthe large particle sized fillers 62 f. In general, a TIM having smallparticle sized fillers has a thickness that is thinner than that ofanother TIM having large particle sized fillers. A thinner TIM betweenthe lid 70 and the initial package structure 50 may easily cause a diecrack.

According to the embodiments of the disclosure, after the lid 70 isattached on the substrate 52 (FIGS. 5B-1 and 5B-2), the thickness of thesecond TIM 64 is the same as that of the first TIM 62 and depends on theparticle size of the fillers 62 f in the first TIM 62. Therefore, thethickness of the second TIM 64 having small particle sized fillers 64 fis increased to avoid die crack. The reliability of the packages 100 isthereby improved. In addition, the thickness of the second TIM 64depending on the large particle sized fillers 62 f in the first TIM 62to become thick can reduce stress concentration phenomenon. Anextra-low-k (ELK) dielectric layer delamination and an edge moldedunderfill crack are thereby prevented. Moreover, the first TIM 62 havinglarge particle sized fillers 62 f positioned in the peripheral region ofthe initial package structure 50 can prevent the second TIM 64 flow outduring performing a high temperature process on the packages 100.Therefore, the reliability of the packages 100 according to theembodiments of the disclosure is enhanced.

According to the embodiments of the disclosure, multiple TIMs, forexample the first TIM 62 and the second TIM 64 are dispensed ondifferent dies or die stacks of the packages 100 to achieve theforegoing advantages. In some embodiments, the first TIM 62 is dispensedon the low-power consuming dies 13 or die stacks 12 in the peripheralregion of the initial package structure 50. The second TIM 64 isdispensed on the high-power consuming die or die stack 10 in the centerregion of the initial package structure 50. The first TIM 62 includesrelatively large particle sized fillers 62 f and has a relatively lowthermal conductivity. The second TIM 64 includes relatively smallparticle sized fillers 64 f and has a relatively high thermalconductivity. The first TIM 62 and the second TIM 64 used in thepackages 100 can reduce stress concentration phenomenon and avoid diecrack. Moreover, the second TIM 64 can be selected to enhance thermalconductivity. Therefore, the heat spreading effect and the reliabilityof the packages 100 according to the embodiments of the disclosure areenhanced.

In addition, the first TIM 62 and the adhesive 60 may be dispensed byusing the same dispenser and the second TIM 64 may be dispensed by usinganother dispenser to eliminate the bottleneck in the fabrication processof IC packages. The throughput of fabricating the packages 100 accordingthe embodiments of the disclosure is thereby enhanced.

In some embodiments, a package is provided. The package includes a dieon a surface of a package component. The package also includes a firstdie stack on the surface of the package component. The package furtherincludes a first thermal interface material (TIM) having a first thermalconductivity and disposed on the first die stack. In addition, thepackage includes a second thermal interface material (TIM) having asecond thermal conductivity and disposed on the die. The first thermalconductivity of the first TIM is different from the second thermalconductivity of the second TIM.

In some embodiments, a package is provided. The package includes a firstdie stack disposed over and bonded to a surface of a substrate. Thepackage also includes a second die stack disposed over and bonded to thesurface of the substrate. The first die stack consumes a relatively lowamount of power than the second die stack. The package further includesa first thermal interface material (TIM) having a first thermalconductivity and dispensed on the first die stack. In addition, thepackage includes a second thermal interface material (TIM) having asecond thermal conductivity and dispensed on the second die stack. Thefirst thermal conductivity of the first TIM is lower the second thermalconductivity of the second TIM.

In some embodiments, a method of fabricating a package is provided. Themethod includes bonding a first die on a surface of a package component,and bonding a second die on the surface of the package component. Themethod also includes bonding the package component on a substrate. Themethod further includes dispensing a first thermal interface material(TIM) on the first die, and dispensing a second thermal interfacematerial (TIM) on the second die. In addition, the method includesdispensing an adhesive on the substrate and around the packagecomponent.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A package, comprising: a die on a surface of apackage component; a first die stack on the surface of the packagecomponent; a first thermal interface material (TIM) having a firstthermal conductivity and disposed on the first die stack; and a secondthermal interface material having a second thermal conductivity anddisposed on the die, wherein the first thermal conductivity of the firstTIM is different from the second thermal conductivity of the second TIM,and the first TIM is in direct contact with the second TIM.
 2. Thepackage as claimed in claim 1, wherein the die consumes a higher amountof power than the first die stack, and the second thermal conductivityof the second TIM is higher than the first thermal conductivity of thefirst TIM.
 3. The package as claimed in claim 2, further comprising: asubstrate, wherein the package component is bonded on a surface of thesubstrate; and an adhesive on the surface of the substrate and aroundthe package component, wherein the first TIM and the adhesive are madeof the same material.
 4. The package as claimed in claim 1, wherein thefirst TIM comprises a first base material and a plurality of firstfillers in the first base material, the second TIM comprises a secondbase material and a plurality of second fillers in the second basematerial, and the first fillers have a particle size that is larger thanthe particle size of the second fillers.
 5. The package as claimed inclaim 1, further comprising: a second die stack on the surface of thepackage component, wherein the first TIM is also on the second diestack.
 6. The package as claimed in claim 1, further comprising: asubstrate, wherein the package component is bonded on a surface of thesubstrate; a passive device on the surface of the substrate; and anadhesive on the surface of the substrate and around the packagecomponent, wherein the passive device is disposed between the adhesiveand the package component.
 7. The package as claimed in claim 6, furthercomprising: a lid attached on the substrate using the adhesive, andattached on the die and the first die stack using the first TIM and thesecond TIM, wherein the passive device is between the lid and thesubstrate.
 8. The package as claimed in claim 7, further comprising: aring between the lid and the adhesive, wherein the ring is attached tothe lid using an additional adhesive.
 9. The package as claimed in claim1, wherein the package component comprises an interposer, a packagesubstrate or a printed circuit board (PCB).
 10. The package as claimedin claim 1, further comprising a molding compound encircling andcontacting the die and the first die stack, wherein the molding compoundis disposed on the package component and top surfaces of the die and thefirst die stack are exposed through the molding compound.
 11. Thepackage as claimed in claim 1, wherein an interface between the firstTIM and the second TIM is on a top surface of the first die stack.
 12. Apackage, comprising: a first die stack disposed over and bonded to asurface of a substrate; a second die stack disposed over and bonded tothe surface of the substrate, wherein the first die stack consumes arelatively low amount of power than the second die stack; a firstthermal interface material (TIM) having a first thermal conductivity anddispensed on the first die stack; and a second thermal interfacematerial having a second thermal conductivity and dispensed on thesecond die stack, wherein the first thermal conductivity of the firstTIM is lower than the second thermal conductivity of the second TIM, andthe second TIM covers the first die stack and the second die stack. 13.The package as claimed in claim 12, further comprising: an adhesive onthe surface of the substrate and around the first die stack and thesecond die stack; and a lid attached on the substrate using theadhesive, and attached on the first die stack and the second die stackusing the first TIM and the second TIM.
 14. The package as claimed inclaim 12, wherein the first TIM comprises a plurality of first fillersdispersed in a first polymer material, the second TIM comprises aplurality of second fillers dispersed in a second polymer material, andthe first fillers have a particle size that is larger than the particlesize of the second fillers.
 15. The package as claimed in claim 12,further comprising: a molding compound encircling and contacting thefirst die stack and the second die stack; an adhesive on the surface ofthe substrate and around the molding compound; and a plurality ofpassive devices on the surface of the substrate and disposed between themolding compound and the adhesive.
 16. A package, comprising: a die overa substrate; a first die stack over the substrate and adjacent to thedie; a first thermal interface material (TIM) disposed on the first diestack; a second thermal interface material disposed on the die, whereinthe second TIM is in direct contact with the die and the first diestack; and an adhesive on the substrate and surrounding the die, thefirst die stack, the first TIM and the second TIM.
 17. The package asclaimed in claim 16, further comprising a second die stack over thesubstrate and adjacent to the first die stack.
 18. The package asclaimed in claim 17, wherein the first TIM extends across the first diestack and the second die stack.
 19. The package as claimed in claim 16,wherein the adhesive layer comprises a plurality of discrete pieces, andthe first TIM and the adhesive are made of the same material.
 20. Thepackage as claimed in claim 17, further comprising a third die stackover the substrate and adjacent to the die, wherein the second TIM is indirect contact with the third die stack.